Extreme ultraviolet light (EUV) photomasks and fabrication methods thereof

ABSTRACT

Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer.

FIELD OF THE INVENTION

The present disclosure relates generally to the field of photomasks usedin the fabrication of semiconductor devices, and more particularly, toextreme ultraviolet light (EUV) photomasks, and fabrication methodsthereof.

BACKGROUND

In the manufacture of integrated circuits (IC), or chips, patternsrepresenting different layers of the chip are created on a series ofreusable photomasks (also referred to herein as masks) in order totransfer the design of each chip layer onto a semiconductor substrateduring the manufacturing process. The masks are used much likephotographic negatives to transfer the circuit patterns for each layeronto a semiconductor substrate. These layers are built up using asequence of processes and translate into the tiny transistors andelectrical circuits that comprise each completed chip. Thus, any defectsin the mask may be transferred to the chip, potentially adverselyaffecting performance. Defects that are severe enough may render themask completely useless. Typically, a set of 15 to 30 masks is used toconstruct a chip and can be used repeatedly.

A mask generally comprises a transparent substrate having an opaque,light-absorbing layer disposed thereon. Conventional masks typicallyinclude a glass or quartz substrate having a layer of chromium on oneside. The chromium layer is covered with an anti-reflective coating anda photosensitive resist. During a patterning process, the circuit designis written onto the mask, for example, by exposing portions of theresist to an electron beam or ultraviolet light, thereby making theexposed portions soluble in a developing solution. The soluble portionof the resist is then removed, allowing the exposed underlying chromiumand anti-reflective layers to be etched (i.e., removed).

With the shrink of critical dimensions (CD), present optical lithographyis approaching a technological limit at the 28 nanometers (nm)technology node. Next generation lithography (NGL) is expected toreplace the current optical lithography method, for example, in the 22nm technology node and beyond. There are several NGL candidates such asextreme ultraviolet (EUV) lithography (EUVL), electron projectionlithography (EPL), ion projection lithography (IPL), nanoimprint, andX-ray lithography. Of these, EUVL is the most likely successor due tothe fact that EUVL has most of the properties of optical lithography,which is a more mature technology as compared with other NGL methods.

However, EUV mask fabrication still has technological challenges toovercome. For example, pellicle is used in the conventional chromiummasks to prevent any unwanted dusts on the mask to be transferred to thechip. However, pellicle is not feasible to the EUV mask because it willabsorb the EUV light. Hence, there is a need to clean the surface of theEUV masks without a pellicle thereon. In addition, there is still a needto monitor the dusts on the surface of the EUV masks.

Thus, there is a need for improved EUV masks and fabrication methods.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is a schematic cross-sectional view illustrating an exemplary EUVmask;

FIGS. 2-8 are various cross-sectional views of embodiments of an EUVmask during various fabrication stages;

FIG. 9 is a flow chart of a method for fabricating an EUV mask accordingto aspects of the present disclosure; and

FIG. 10 is a flow chart of a method for fabricating an integratedcircuit device by using an EUV mask according to aspects of the presentdisclosure.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of theinvention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a feature on, connected to, and/or coupled toanother feature in the present disclosure that follows may includeembodiments in which the features are formed in direct contact, and mayalso include embodiments in which additional features may be formedinterposing the features, such that the features may not be in directcontact. In addition, spatially relative terms, for example, “lower,”“upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,”“top,” “bottom,” etc. as well as derivatives thereof (e.g.,“horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of thepresent disclosure of one features relationship to another feature. Thespatially relative terms are intended to cover different orientations ofthe device including the features.

FIG. 1 is a schematic cross-sectional view illustrating an EUV photomask100. In some embodiments, the EUV photomask 100 include a substrate 110,a first reflective layer 112 on the substrate 110, an intervening layer114 on the first reflective layer 112, a second reflective layer 116 onthe intervening layer 114, a capping layer 118 on the second reflectivelayer 116, and an absorber 126 in an opening penetrating the cappinglayer 118 and at least a portion of the second reflective layer 116. Insome embodiments, the absorber 126 has a top surface lower than the topsurface of the capping layer 118. In the present embodiment, theabsorber 126 has a top surface lower than the top surface of the secondreflective layer 116.

The substrate 110 may be any size suitable for use as a photomask. Inone embodiment, the substrate 110 has a rectangular shape with sidesbetween about 5 inches to about 9 inches in length. In anotherembodiment, the substrate 110 has a thickness ranging about 0.15 inchesand about 0.25 inches. In other embodiment, the substrate 110 is about0.25 inches thick. In some embodiments, the substrate 110 has a lowthermal expansion coefficient (specifically 0±0.05×10−7/° C.,particularly preferably 0±0.03×10−7/° C. at 20° C.), and be excellent insmoothness, flatness and durability to a cleaning liquid used forcleaning the mask blank or the photomask after the formation of apattern. The substrate 110 typically comprises a silicon-based materialhaving low thermal expansion coefficient, such as quartz (i.e., silicondioxide, SiO2), and the like.

The first reflective layer 112 can achieve a high reflectivity to EUVlight. For example, the first reflective layer 112 has reflectivity upto 65 40% when the surface of the first reflective layer 112 isirradiated by the EUV light having wavelength of around 13.5 nm. In thepresent embodiment, a multilayered reflective film formed by laminatingalternately a layer of high refractive index and a layer of lowrefractive index plural times is employed as the first reflective layer112. In some embodiments, Mo is employed for the layer of low refractiveindex and Si is used for the layer of high refractive index for formingthe multilayered reflective film of the first reflective layer 112.Namely, a Mo/Si multilayered reflective film is formed for forming thefirst reflective layer 112. In one embodiment, the first reflectivelayer 112 may comprise alternating Mo and Si layers ranging betweenabout 20 pairs and about 40 pairs. Each pair of the Mo and Si layers maycomprise a Mo layer with a thickness of about 3 nm and a Si layer with athickness of about 4 nm.

In alternative embodiments, the multilayered reflective film is a Ru/Simultilayered reflective film, a Mo/Be multilayered reflective film, a Mocompound/Si compound multilayered reflective film, a Si/Mo/Rumultilayered reflective film, a Si/Mo/Ru/Mo multilayered reflective filmor a Si/Ru/Mo/Ru multilayered reflective film.

The intervening layer 114 acts as an etch stop layer when forming theopening in the second reflective layer 116 by an etching process. Insome embodiments, an etching selectivity between the second reflectivelayer 116 and the intervening layer 114 during the etching process forforming the opening is greater than about 10. In some embodiments, theintervening layer 114 includes Cr, Ru, or combinations thereof.

The second reflective layer 116 can achieve a high reflectivity to EUVlight. For example, the second reflective layer 116 has reflectivity upto 40% when the surface of the second reflective layer 116 is irradiatedby the EUV light having wavelength of around 13.5 nm. In the presentembodiment, a multilayered reflective film formed by laminatingalternately a layer of high refractive index and a layer of lowrefractive index plural times is employed as the second reflective layer116. In the present embodiment, the second reflective layer 116 includesthe multilayered reflective film same as the first reflective layer 112,e.g., Mo/Si multilayered reflective film. In some embodiments, a ratioof the thickness of the second reflective layer 116 to the thickness ofthe first reflective layer 112 is ranging between about 0.25 andabout 1. The second reflective layer 116 may comprise alternating Mo andSi layers ranging between about 10 pairs and about 20 pairs. Each pairof the Mo and Si layers may comprise a Mo layer with a thickness ofabout 3 nm and a Si layer with a thickness of about 4 nm. In the presentembodiment, the total thickness of the second reflective layer 116 andthe first reflective layer 112 is ranging between about 200 nm and about400 nm.

The capping layer 118 acts as a capping layer and/or a buffer layerbetween the second reflective layer 116 and a hard mask layer present inan intermediate process for forming photomask. In some embodiments, thecapping layer 118 is a silicon (Si) layer, ruthenium (Ru) layer, orRu-containing layer. The capping layer 118, for example, has a thicknessranging between about 1 nm and about 10 nm.

In some embodiments, the absorber 126 has a bottom surface that contactsthe top surface of the intervening layer 114 and has a top surface lowerthan the top surface of the capping layer 118. A height difference D ispresent between the top surfaces of the absorber 126 and the cappinglayer 118. In some embodiments, the height difference D is greater thanabout 20 nm to ensure the particles on the absorber 126 are trappedstrongly during wafer lithography process. In the present embodiment,the height difference D ranges between about 20 nm and about 50 nm. Theabsorber 126 has a thickness T. In some embodiments, the thickness T isgreater than about 20 nm to prevent light leakage or poor contrastduring a wafer lithography process. In an alternative embodiment, thethickness T is less than about 150 nm to prevent the difficulty offabricating the mask. In the present embodiment, the thickness T rangesbetween about 20 nm and about 150 nm.

The absorber 126 is an opaque, light-shielding layer. In one embodiment,the absorber 126 comprises tantalum-based materials with essentially nooxygen, such as tantalum silicide-based materials (hereinafter TaSi),nitrogenized tantalum boride-based materials (hereinafter TaBN), andtantalum nitride-based materials (hereinafter TaN). In anotherembodiment, the absorber 126 comprises tantalum- and oxygen-basedmaterials, such as oxidized and nitrogenized tantalum and silicon-basedmaterials (hereinafter TaSiON), tantalum boron oxide-based materials(hereinafter TaBO), and oxidized and nitrogenized tantalum-basedmaterials (hereinafter TaON).

FIGS. 2-8 are schematic cross-sectional views illustrating an exemplaryprocess flow for forming an EUV photomask. Items of FIGS. 2-8 that arethe same items in FIG. 1 are indicated by the same reference numerals,increased by 100. With reference to FIGS. 2-8 and 9, an EUV photomask200 and a method 300 are collectively described below.

Referring to FIGS. 2 and 9, the method 300 begins at step 302 wherein afirst reflective layer 212 is formed over a substrate 210. In someembodiments, an intervening layer 214 is formed on the first reflectivelayer 212, a second reflective layer 216 is formed on the interveninglayer 214, and a capping layer 218 is formed over the second reflectivelayer 216. In some embodiments, a hard mask layer 220 is formed over thecapping layer 218. In some embodiments, the substrate 210 is arectangular shape substrate with sides ranging between about 5 inchesand about 9 inches in length and has a thickness ranging between about0.15 inches and 0.25 inches. In some embodiments, the substrate 210 hasa low thermal expansion coefficient (specifically 0±0.05×10−7/° C.,particularly preferably 0±0.03×10−7/° C. at 20° C.), and be excellent insmoothness, flatness and durability to a cleaning liquid used forcleaning the mask blank or the photomask after the formation of apattern. The substrate 210 typically includes a silicon-based materialhaving low thermal expansion coefficient, such as quartz (i.e., silicondioxide, SiO2), and the like.

The first reflective layer 212 can achieve a high reflectivity to EUVlight. For example, the first reflective layer 212 has reflectivity upto 40% when the surface of the first reflective layer 212 is irradiatedby the EUV light having wavelength of around 13.5 nm. In someembodiments, the first reflective layer 212 is a multi-material layer.In some embodiments, the multilayered reflective film is formed bylaminating alternately a layer of high refractive index and a layer oflow refractive index plural times. In the present embodiment, Mo isemployed for the layer of low refractive index and Si is used for thelayer of high refractive index for forming the multilayered reflectivefilm of the first reflective layer 212. Namely, a Mo/Si multilayeredreflective film is formed for forming the first reflective layer 212. Inone embodiment, the first reflective layer 212 may comprise alternatingMo and Si layers ranging between about 20 pairs and about 40 pairs. Eachpair of the Mo and Si layers may comprise a Mo layer with a thickness ofabout 3 nm and a Si layer with a thickness of about 4 nm.

In alternative embodiments, the multilayered reflective film is a Ru/Simultilayered reflective film, a Mo/Be multilayered reflective film, a Mocompound/Si compound multilayered reflective film, a Si/Mo/Rumultilayered reflective film, a Si/Mo/Ru/Mo multilayered reflective filmor a Si/Ru/Mo/Ru multilayered reflective film. In some embodiments, thefirst reflective layer 212 is formed by a deposition process, includingchemical vapor deposition (CVD), physical vapor deposition (PVD), atomiclayer deposition (ALD), and/or other suitable process.

The intervening layer 214 may function as an etch stop layer during asubsequent etching process. In some embodiments, the intervening layer214 includes Cr, Ru, or a combination thereof. In the presentembodiment, the intervening layer 214 has a thickness ranging betweenabout 2 nm and about 7 nm. In alternative embodiments, the interveninglayer 214 has a thickness about 2.5 nm. In some embodiments, theintervening layer 214 is formed by a deposition process, including CVD,PVD, ALD, and/or other suitable process.

The second reflective layer 216 can achieve a high reflectivity to EUVlight. For example, the second reflective layer 216 has reflectivity upto 30% when the surface of the second reflective layer 216 is irradiatedby the EUV light having wavelength of around 13.5 nm. In the presentembodiment, a multilayered reflective film formed by laminatingalternately a layer of high refractive index and a layer of lowrefractive index plural times is employed as the second reflective layer216. In the present embodiment, the second reflective layer 216 includesthe multilayered reflective film same as the first reflective layer 212,e.g., Mo/Si multilayered reflective film. In some embodiments, a ratioof the thickness of the second reflective layer 216 to the thickness ofthe first reflective layer 212 ranges between about 0.25 and about 1.

The second reflective layer 216 may comprise alternating Mo and Silayers ranging between about 10 pairs and about 20 pairs. Each pair ofthe Mo and Si layers may comprise a Mo layer with a thickness of about 3nm and a Si layer with a thickness of about 4 nm. In the presentembodiment, the total thickness of the second reflective layer 216 andthe first reflective layer 212 is ranging between about 200 nm and about400 nm.

The capping layer 218 may function as a capping layer and/or a bufferlayer interposed between the second reflective layer 216 and the hardmask layer 220. In some embodiments, the capping layer 218 is a silicon(Si) layer, ruthenium (Ru) layer, Ru-containing layer. In someembodiments, the capping layer 218 has a thickness ranging between about1 nm and about 10 nm. In alternative embodiments, the capping layer 218has a thickness about 2.5 nm. In some embodiments, the capping layer 218is formed by a deposition process, including CVD, PVD, ALD, and/or othersuitable process.

In some embodiments, the hard mask layer 220 includes Ru, RuSi, or acombination thereof. In one embodiment, the hard mask layer 220 has athickness ranging between about 2 nm and about 15 nm. In anotherembodiment, the thickness of the hard mask layer 220 is about 5 nm. Insome embodiments, the hard mask layer 220 is formed by CVD, PVD, ALD,and/or other suitable process.

Referring to FIGS. 3, 4 and 9, the method 300 continues with step 304wherein the second reflective layer 216 is subjected to a patterningprocess to form an opening 224 therein. In the present embodiment, theopening 224 is located within the hard mask layer 220, the capping layer218, and the second reflective layer 216 (FIG. 4). The patterningprocess may include forming photoresist features 222 over the hard masklayer 220 and then removing the portion of the hard mask layer 220uncovered by the photoresist features 222.

In some embodiments, the process for forming the photoresist features222 includes forming a layer of photoresist (not shown) over the hardmask layer 220 by a suitable process, such as spin-on coating, and thenexposing and developing the layer of photoresist to form the photoresistfeatures 222 separated with a space (FIG. 3). The photoresist features222 partially expose the underlying hard mask layer 220. Additionally,an anti-reflective coating (ARC) layer (not shown) may be optionallyformed between the hard mask layer 220 and the layer of photoresist toenhance the patterning process.

Referring to FIG. 4, a removing process is performed to remove theportion of the hard mask layer 220 uncovered by the photoresist features222 and thereby transfer the patterns of the photoresist features 222 tothe underlying hard mask layer 220. In some embodiments, the removingprocess includes an etching process performed using halogen-based gas,e.g., Cl2, CHF3, CH3F, C4F8, CF4, SF6, CF3Cl, or mixtures thereof toremove the uncovered portion of the hard mask layer 220. Then theetching process stops on the underlying capping layer 218 and expose aportion of the capping layer 218.

Still referring to FIG. 4, a portion of the capping layer 218 and thesecond reflective layer 216 are then removed by a single or multipleetching processes to form the opening 224. In some embodiments, theintervening layer 214 functions as an etch stop layer during the etchingprocess thereby the removing process stops on the intervening layer 214.In some embodiments, an etching selectivity between the secondreflective layer 216 and the intervening layer 214 during the etchingprocess for forming the opening 224 is greater than about 10 to ensurethe controllability of the etching process.

In the present embodiment, the capping layer 218 and the secondreflective layer 216 are patterned by a single dry etching process. Insome embodiments, the single dry etching process is performed usingchlorine-based gas, e.g., Cl2 or CCl4, to remove the portion of cappinglayer 218 uncovered by the patterned hard mask layer 220 to expose aportion of the underlying second reflective layer 216, and at least aportion of the underlying second reflective layer 216 is continuouslyremoved after the removal of the capping layer 218. In anotherembodiment, at least a portion of the underlying second reflective layer216 is removed by a separate etching process different from the etchingprocess for patterning the capping layer 218. In some embodiments, thesecond reflective layer 216 is removed by using Cl2, F2, or mixturethereof. In some embodiments, the exposed portion of second reflectivelayer 216 is completely removed and stops on the surface of theintervening layer 214. In alternative embodiments, the exposed portionof second reflective layer 216 is partially removed and stops within thesecond reflective layer 216.

The photoresist features 222 may be removed after the etching process ofthe hard mask layer 220, after the etching process of the capping layer218, or after the etching process of the second reflective layer 216. Insome embodiments, the removal of the photoresist features 222 isperformed by implementing a wet stripping and/or plasma ashing known inthe art. For example, an oxygen plasma ashing may be implemented toremove the photoresist features 218.

Referring to FIGS. 5 and 9, the method 300 continues with step 306wherein an absorber layer 226 is filled in the opening 224 and above thetop surface of the hard mask layer 220. The absorber layer 226 is anopaque, light-shielding layer and may have a thickness ranging betweenabout 20 nm and about 100 nm. In one embodiment, the absorber layer 226comprises tantalum-based materials with essentially no oxygen, such astantalum silicide-based materials (hereinafter TaSi), nitrogenizedtantalum boride-based materials (hereinafter TaBN), and tantalumnitride-based materials (hereinafter TaN). In another embodiment, theabsorber layer 226 comprises tantalum- and oxygen-based materials, suchas oxidized and nitrogenized tantalum and silicon-based materials(hereinafter TaSiON), tantalum boron oxide-based materials (hereinafterTaBO), and oxidized and nitrogenized tantalum-based materials(hereinafter TaON).

In some embodiments, the absorber layer 226 is formed by a depositionprocess. The deposition, for example, includes PVD such as sputteringand evaporation; plating; CVD such as plasma enhanced CVD (PECVD),atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), high densityplasma CVD (HDPCVD), atomic layer CVD (ALCVD), other suitable depositionprocesses, and/or combinations thereof. In alternative embodiments, theabsorber layer 226 is formed by a spin coating process. In the presentembodiment, the absorber layer 226 is formed by a deposition processwith an uneven surface 226S (FIG. 5).

Referring to FIG. 6, a planarization layer 228 is formed on the absorberlayer 226 with a planarized surface. In some embodiments, theplanarization layer 228 is Ag2O3, Si-containing layer, Carbon-containinglayer, or combinations thereof. The planarization layer 228, forexample, is formed by a spin coating process. In the present embodiment,the planarization layer 228 has an etching rate similar to an etchingrate of the underlying absorber layer 226 during a subsequent etchingprocess. In some embodiments, the planarization layer 228 has athickness that entirely covers the absorber layer 226. In the presentembodiment, the planarization layer 228 has a thickness that ranges fromabout 30 nm to about 150 nm. In alternative embodiments, theplanarization layer 228 can be omitted if a planarized surface hasalready achieved by the absorber layer 226, for example, the absorberlayer 226 is formed by a spin coating process.

Referring to FIGS. 7 and 9, the method 300 continues with step 308wherein a process is provided to remove at least a portion of theabsorber layer 226, while leaving another portion of the absorber layer226 to form an absorber 226′ in the second reflective layer 216. In thepresent embodiment, the planarization layer 228 is removed beforeremoving the portion of the absorber layer 226. The processes forremoving the planarization layer 228 and the absorber layer 226, forexample, is performed using a single etching process. The removedportion of the absorber layer 226 includes, for example, the portion ofthe absorber layer 226 above the opening 224 and above the hard masklayer 220. In some embodiments, a portion of the absorber layer 226 inthe opening 224 is removed to form the absorber 226′ with a top surfacesubstantially lower than the top surface of the capping layer 218. Aheight difference D is present between the top surface of the absorber226′ and the top surface of capping layer 218. In the presentembodiment, the absorber 226′ has a top surface substantially lower thanthe top surface of the second reflective layer 216.

The height difference D, for example, is greater than about 20 nm tosecure the particles on the absorber 226′ against falling on thereflective layer 216 during wafer lithography process. In the presentembodiment, the height difference D ranges between about 20 nm and about50 nm. In some embodiments, the absorber 226′ has a thickness T greaterthan about 20 nm to prevent light leakage or poor contrast during waferlithography process. In an alternative embodiment, the thickness T isless than about 150 nm to prevent the difficulty of fabricating themask. In the present embodiment, the thickness T ranges between about 20nm and about 150 nm.

In some embodiments, the removing process includes a dry etching processby CF4, Cl2, or a mixture thereof. In alternative embodiment, theremoving process includes a chemical-mechanical polish (CMP) process byusing fluoride-base slurry. In other embodiment, the removing process isconducted by a CMP process first to remove a portion of the absorberlayer 226 and leave some of the absorber layer 226 above the opening 224and the hard mask layer 220. Then, a dry etching process is provided toremove the additional absorber layer 226 over and in the opening 224,while leaving another portion of the absorber layer 226 in the opening224 to form the absorber 226′. During the CMP or the dry etchingprocess, the hard mask layer 220 may act as a stop layer to stop the CMPor the dry etching process thereon. The top surface of the absorber 226′may be substantially planarized when the planarization layer 228 has anetching rate similar to the etching rate of the absorber layer 226during the dry etching process. For example, a ratio of the etching rateof the planarization layer 228 to the etching rate of the absorber layer226 ranges from about 0.8 to about 1.2.

Referring to FIG. 8, the hard mask layer 220 is removed after formingthe absorber 226′. In some embodiments, the removing process includes adry etching process. The dry etching process is performed using, forexample, halogen-based etching gas, including F-containing gas, e.g.,CF4, SF6, CHF3, Cl-containing gas, e.g., Cl2, CCl4, or Br-containinggas, e.g., HBr, Br2. Dilute gas, such as He or Ar, may be added in theetching gas during the etching process. In alternative embodiments, theremoving process is wet etching process or CMP.

Referring to FIG. 10, a flow chart of a method 400 for fabricating anintegrated circuit device by using an EUV mask is described below. Themethod 400 begins at step 402 wherein a semiconductor substrate having amaterial layer is provided. The method 400 continues with step 404 toform a photoresist layer over the material layer. Then, the method 400continues with step 406 to pattern the photoresist layer by using an EUVmask as described above in a lithography process. The method 400continues with step 408 to pattern the material layer by using thepatterned photoresist layer as an etch mask.

It is noted that the EUV masks with the planarized surface are easilycleaned. In addition, dust-monitoring processes are easily performed onthe EUV masks having the planarized surface. Furthermore, opticalperformance, e.g., particle issue, may be improved by adopting theabsorber with a top surface lower than a top surface of the cappinglayer or the reflective layer to secure the particles on the absorberagainst falling on the capping layer or the reflective layer duringwafer lithography process.

It is noted that the integrated circuit devices processed by using theEUV masks are likely to prevent unwanted dusts or particles on thereflective layer to be transferred to the chip.

In one embodiment, a method of fabricating an extreme ultravioletphotomask, includes providing a mask comprising, in order, a substrate,a reflective layer, and a capping layer; forming an opening in thecapping layer and at least a portion of the reflective layer; forming anabsorber layer in the opening and over the top surface of the cappinglayer; and removing at least a portion of the absorber layer, whileleaving another portion of the absorber layer to form a absorber. Theabsorber has a top surface lower than a top surface of the cappinglayer.

In another embodiment, an extreme ultraviolet photomask, includes areflective layer over a substrate; a capping layer over the reflectivelayer; and an absorber in the capping layer and the reflective layer. Atop surface of the absorber is lower than a top surface of the cappinglayer.

In still another embodiment, a method for forming an integrated circuitincludes forming a photomask by forming a reflective layer over asubstrate, forming a capping layer over the reflective layer, andforming an absorber in the capping layer and the reflective layer;forming a layer on a substrate; and patterning the layer using thephotomask in a photolithography step. A top surface of the absorber islower than a top surface of the capping layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of fabricating an extreme ultraviolet photomask, comprising: providing a mask comprising, in order, a substrate, a reflective layer, and a capping layer; forming an opening in the capping layer and at least a portion of the reflective layer; forming an absorber layer in the opening and over a top surface of the capping layer; and removing at least a portion of the absorber layer, while leaving another portion of the absorber layer to form an absorber, wherein the absorber has a top surface lower than a top surface of the capping layer.
 2. The method of claim 1, wherein the absorber has the top surface lower than a top surface of the reflective layer.
 3. The method of claim 1, wherein a height difference of the top surface of the absorber and the top surface of the capping layer ranges between about 20 nm and about 50 nm.
 4. The method of claim 1, wherein the reflective layer comprises alternating Mo and Si layers ranging between about 20 pairs and about 80 pairs.
 5. The method of claim 1, further comprising: forming an underlying reflective layer over the substrate; and forming an intervening layer between the underlying reflective layer and the reflective layer.
 6. The method of claim 5, wherein the intervening layer includes Cr, Ru, or a combination thereof.
 7. The method of claim 5, wherein the absorber is formed on the intervening layer.
 8. The method of claim 5, wherein the underlying reflective layer comprises alternating Mo and Si layers ranging between about 20 pairs and about 40 pairs.
 9. The method of claim 5, wherein a thickness ratio of the reflective layer to the underlying reflective layer ranges between about 0.25 and about
 1. 10. The method of claim 1, further comprising forming a planarization layer over the absorber layer.
 11. The method of claim 10, wherein the planarization layer is Ag₂O₃, Si-containing layer, Carbon-containing layer, or combinations thereof.
 12. The method of claim 10, further comprising removing the planarization layer before removing the at least a portion of the absorber layer.
 13. The method of claim 1, wherein the absorber layer is TaSi, TaBN, TaN, TaSiON, TaBO, or TaON.
 14. The method of claim 1, wherein the absorber has a thickness ranging between about 20 nm and about 150 nm.
 15. The method of claim 1, further comprising forming a hard mask layer over the capping layer.
 16. The method of claim 15, further comprising removing the hard mask after forming the absorber.
 17. The method of claim 1, wherein the step of removing includes a CMP process and/or a dry etching process.
 18. An extreme ultraviolet photomask, comprising: a reflective layer over a substrate; a capping layer over the reflective layer; and an absorber in the capping layer and the reflective layer, wherein a top surface of the absorber is lower than a top surface of the capping layer.
 19. A method for forming an integrated circuit comprising: forming a photomask by forming a reflective layer over a substrate; forming a capping layer over the reflective layer; and forming an absorber in the capping layer and the reflective layer, wherein a top surface of the absorber is lower than a top surface of the capping layer; forming a layer on a substrate; and patterning the layer using the photomask in a photolithography step. 